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ug474-7Series-CLB.pdf
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ug474-7Series-CLB.pdf
7 Series FPGAs
Configurable Logic Block
User Guide
UG474 (v1.8) September 27, 2016
7 Series FPGAs CLB User Guide www.xilinx.com UG474 (v1.8) September 27, 2016
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Revision History
The following table shows the revision history for this document.
Date Version Revision
03/01/2011 1.0 Xilinx Initial release.
03/28/2011 1.1 Added devices XC7K355T, XC7K420T, and XC7K480T to Table 1-3. Portions of the text
have been revised for clarity.
09/30/2011 1.2 Added last sentence under 7 Series CLB Features. Added Table 1-3 and Table 1-4.
Updated CLB features in Table 1-3. Added first sentence under CLB Arrangement,
added ASMBL Architecture section, and CLB Slices heading. Added last paragraph
under Carry Logic. Added lasts sentence under Using Carry Logic. Added second
sentence under Slice Multiplexer Timing Parameters. Modified Table 5-2, Table 5-4, and
Table 5-5 for clarity. Added Devices Using Stacked Silicon Interconnect (SSI) Technology
section.
01/30/2012 1.3 Revised Table 1-2. Added fifth paragraph under Distributed RAM (Available in SLICEM
Only). Clarified last paragraph under Global Controls GSR and GTS.
11/05/2012 1.4 Changed “uniformity” to “optimized” in last bullet under 7 Series CLB Features.
Changed “unified” to “scalable” in first sentence under Device Resources. Deleted
7A350T device from Table 1-2. Deleted 7V1500T and 7VH290T devices from Table 1-4.
Added reference to 7 Series FPGA Libraries Guide to Distributed RAM (Available in
SLICEM Only), Shift Registers (Available in SLICEM Only), and Flip-Flop Primitives.
Changed “T
CEO
” to “T
CECK
” in Figure 5-2 and first bullet under General Timing
Characteristics.
UG474 (v1.8) September 27, 2016 www.xilinx.com 7 Series FPGAs CLB User Guide
08/6/2013 1.5 Added Artix®-7 devices. Updated references to implementation tools.
08/11/2014 1.6 Revised footnotes in Table 1-2 through Table 1-4. Revised polarity from independent to
programmable in Control Signals, page 22. Added Primitive column to Table 2-3 and
removed footnotes. Renamed or made minor revisions to Figure 2-6 through Figure 2-14.
Revised sections Clock – WCLK, page 49, Clock – CLK, page 50, and Clock - C, page 51.
11/17/2014 1.7 Updated Table 1-2 for new Artix 7A15T device.
09/27/2016 1.8 Added Spartan®-7 device family (updated Preface and added Table 1-1). Added
Artix®-7 7A12T and 7A25T devices to Table 1-2.
Date Version Revision
7 Series FPGAs CLB User Guide www.xilinx.com 5
UG474 (v1.8) September 27, 2016
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 1: Overview
CLB Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7 Series CLB Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Recommended Design Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pinout Planning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 2: Functional Details
CLB Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Slice Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Look-Up Table (LUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Storage Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Distributed RAM (Available in SLICEM Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Shift Registers (Available in SLICEM Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chapter 3: Design Entry
Design Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Using the CLB Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Chapter 4: Applications
Distributed RAM Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Shift Register Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Carry Logic Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 5: Timing
CLB General Slice Timing Model and Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
CLB Slice Multiplexer Timing Model and Parameters. . . . . . . . . . . . . . . . . . . . . . . . 60
CLB Slice Carry-Chain Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . 61
Table of Contents
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