广东华冠 HGSEMI EEPROM 扩展器件库 I2C扩展器件库 & 芯片数据手册

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广东华冠 HGSEMI EEPROM 扩展器件库 I2C扩展器件库 ------HG24C02.iic ------HG24C02.pdf ------HG24C04.iic ------HG24C04.pdf ------HG24C04.iic ------HG24C04.pdf ------HG24C08.iic ------HG24C08.pdf ------HG24C16.iic ------HG24C16.pdf ------HG24C32.iic ------HG24C32.pdf ------HG24C64.iic ------HG24C64.pdf ------HG24C128.iic ------HG24C128.pdf ------HG24C256.iic ------HG24C256.pdf ------HG24C512.iic ------HG24C512.pdf ------HG24C1024.iic ------HG24C1024.pdf ------HG24C256C.iic ------HG24C256C.pdf .............

HG24C256C

http://www.hgsemi.com.cn 2016 DEC

256-Kbit I

C-compatible Serial EEPROM

Features

 Supply Voltage: 1.7V to 5.5V

 2-wire Serial Interface I

C Compatible

- 400 kHz and High Speed 1MHz Transfer Rate Compatibility

 Byte and Page (up to 64 Bytes) Write Mode

- Partial Page Writes Allowed

 Self-timed Write Cycle (3ms Maximum)

 Hardware Write Protection on the Whole Memory Array

 Additional 64-byte Write Lockable Page and 128-bit Unique ID

 Schmitt Trigger, Filtered Inputs for Noise Suppression

 Low Operating Current

- Write Current: 1mA (Maximum)

- Read Current: 0.5mA (Maximum)

Standby Current: 1μA (Maximum)

 High Reliability

- Endurance: 2,000,000 Write Cycles

- Data Retention: 100 Years

 Operating Temperature Range: -40°C to +105°C

 Green Packaging Options (Pb/Halide-free/RoHS Compliant)

- DIP-8,TSSOP-8, SOP-8,MSOP-8,DFN-8 3*3

Ordering Information

DEVICE

Package Type

MARKING

Packing

Packing Qty

HG24C256CN

DIP-8

24C256C

TUBE

2000pcs/box

HG24C256CM/TR

SOP-8

24C256C

REEL

2500pcs/reel

HG24C256CMM/TR

MSOP-8

C256C

REEL

3000pcs/reel

HG24C256CMT/TR

TSSOP-8

C256C

REEL

3000pcs/reel

HG24C256CDQ/TR

DFN-8 3*3

C256C

REEL

3000pcs/reel

DIP-8

SOP-8

TSSOP-8

MSOP-8

DFN-8 3*3

HG24C256C

http://www.hgsemi.com.cn 2016 DEC

Description

The HG24C256C is a 256-Kbit I

C-compatible Serial EEPROM (Electrically Erasable Programmable Memory) device.

The device is designed to operate in a supply voltage range of 1.7V to 5.5V, with a maximum of 1MHz transfer rate. The

operating temperature range is from -40°C to +105°C. The device incorporates a Write Protection pin used for hardware

Write Protection on the whole memory array.

The Serial EEPROM memory is organized as 512 pages of 64 bytes each, totaling 32768*8 bits. The device offers an

additional 64-byte Identification Page for users to store sensitive application parameters. This page can be permanently

locked in Read-only mode after the application data is written intothe Identification Page. The HG24C256C also offers a

separate memory block containing a factory programmed 128-bit Unique ID. This block is in Read-onlymode and can be

accessed to by sending a specific Read command.

The HG24C256C is delivered in Lead-free green packages: DIP-8, TSSOP-8, SOP-8, MSOP-8,DFN-8 3*3.

Pin Configuration

DIP-8/SOP-8/TSSOP-8/MSOP-8 DFN-8 3*3

Pin Descriptions

Symbol

Type

Name and Function

Input

Device Address Inputs: The E0, E1, and E2 pins are used to select the device address and

correspond to the three Least-Significant Bits of the l

C seven-bit slave address. These pins

can

be directly connected to V

or GND in any combination, allowing up to eight devices on

the

same bus.

SDA

Input/Output

Serial Data: The SDA pin is an open-drain bidirectional input/output pin used to serially

transfer data to and from the device.

SCL

Input

Serial Clock: The SCL pin is used to provide a clock to the device and is used to control the

flow of data to and from the device. Command and input data present on the SDA pin is

always latched in on the rising edge of SCL, while output data on the SDA pin is always

clocked out on the falling edge of SCL.

Power

Device Power Supply: The V

pin is used to supply the source voltage to the device.

Operations at invalid V

voltages may produce spurious results and should not be

attempted.

GND

Power

Ground: The ground reference for the power supply. GND should be connected to the

systemground.

Input

Write Protection: The WP pin is used to write protect the entire contents of the memory.

When the WP pin is connected to Power Supply, the entire memory array becomes

Write-protected, that is, the device becomes Read-only. When the WP pin is connected to

Ground or left floating,Write operations are enabled.

When the WP pin is driven high, the device address byte and the word address bytes are

acknowledged, data bytes are not acknowledged.

(Top View)

HG24C256C

http://www.hgsemi.com.cn 2016 DEC

Functional Block Diagram

Hardware

Address

Comparator

Memory System

Control Module

Power On

Reset

Generator

High Voltage Generation Circuit

256-Kbit EEPROM Array

Address Register

and Counter

Column Decoder

SCL

Data Register

OUT

Data & ACK

I/O Control

Start

Stop

Detector

NMOS

GND

SDA

Row Decoder

HG24C256C

http://www.hgsemi.com.cn 2016 DEC

Device Communication

The HG24C256C operates as a slave device and utilizes a 2-wire serial interface to communicate with the Master. The Master

initiates and controls all Read and Write operations to the slave devices on the serialbus, and both the Master and the slave

devices can transmit and receive data on the bus.

The serial interface is comprised of just two signal lines: the Serial Clock (SCL) and the Serial Data (SDA). Data is always

latched into the HG24C256C on the rising edge of SCL and is always output from the deviceon the falling edge of SCL. Both

the SCL pin and SDA pin incorporate integrated spike suppression filtersand Schmitt Triggers to minimize the effects of input

spikes and bus noise.

All command and data information is transferred with the Most Significant Bit (MSB) first. During the bus communication, one

data bit is transmitted every clock cycle, and after eight bits of data has been transferred, the receiving device must respond

with an acknowledge or a no-acknowledge response bit during a ninth clock cycle generated by the Master. Therefore, nine

clock cycles are required for every one byte of data transferred. There is no unused clock cycle during any Read or Write

operation, so theremust not be any interruptions or breaks during the data stream.

During data transfers, data on the SDA pin must only change while SCL is low, and the data must remainstable while SCL is

high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will occur. The number of data

bytes transferred between a Start and a Stop condition is not limited and is determined by the Master.

Start Condition

A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is stable in Logic 1 state. The

Start condition must precede any command as the Master uses a Start condition to initiate any data transfer sequence (see

Figure 1). The HG24C256C will continuously monitor the SDA and SCL pins for a Start condition, and the device will not

respond unless one is given.

Figure 1 Start, Stop, and ACK

Stop Condition

A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable inLogic 1 state (see

Figure 1). A stop condition terminates communication between the HG24C256C and the Master. A Stop condition at the end of

a Write command triggers the EEPROM internal write cycle. Otherwise, the HG24C256C subsequently returns to Standby

mode after receiving a Stop condition.

Acknowledge (ACK)

After each byte of data is received, the HG24C256C should acknowledge to the Master that it has received the data byte

successfully. This is accomplished by the Master first releasing the SDA line and providing the ACK/NACK clock cycle (a ninth

clock cycle for every byte). During the ACK/NACK clock cycle, the HG24C256C must output Logic 0 as ACK for the entire clock

cycle so that the SDA line must be stable in Logic 0 state during the entire high period of the clock cycle (see Figure 1).

HG24C256C

http://www.hgsemi.com.cn 2016 DEC

Standby Mode

The HG24C256C features a low-power Standby mode which is enabled:

(1) Upon power-up;

(2)

After the receipt of a Stop condition in Read operation;

(3) The completion of any internal operations.

Software Reset

After an interruption in protocol, power loss, or system reset, any 2-wire part can be reset by following these steps: (1) Create a

Start condition; (2) Clock nine cycles; (3) Create another Start condition followedby a Stop condition (see Figure 2).

Figure 2 2-wire Software Reset

Device Reset and Initialization

The HG24C256C incorporates a Power-On Reset (POR) circuit to prevent inadvertent operations during power-up. On a cold

power-up, the device does not respond to any instructions until the supply voltage reaches the internal power-on reset

threshold voltage (V

POR

). The supply voltage must rise continuously between V

POR

and V

(Min) without any ring back to

ensure a proper power-up. Once the supply voltage passes V

POR

, the device is reset and enters Standby mode. However, no

protocol should be issued to the device until a valid and stable supply voltage is applied for the time specified by the t

INIT

parameter. The supply voltage must remain stable and valid until the end of the protocol transmission, and for a Write

instruction, until the end of the internal write cycle (see Figure 3).

This POR behavior is bi-directional. It protects the HG24C256C against brown-out failure caused by a temporary loss of power.

In a similar way, as soon as the supply voltage drops below the internal brown-out reset threshold voltage (V

BOR

), the device is

reset and stops responding to any instructions (see Figure 3). The V

BOR

level is set below the V

POR

level.

Parameters related to power-up and power-down conditions are listed in Table 1.

Figure 3 Power-up and Power-down Timing

资源文件列表:

广东华冠 HGSEMI EEPROM器件库.zip 大约有28个文件

广东华冠 HGSEMI/0.readme（使用前必读）.txt 1.34KB
广东华冠 HGSEMI/HG24C02.iic 5.33KB
广东华冠 HGSEMI/HG24C02.pdf 648.67KB
广东华冠 HGSEMI/HG24C04.iic 5.33KB
广东华冠 HGSEMI/HG24C04.pdf 648.67KB
广东华冠 HGSEMI/HG24C08.iic 5.33KB
广东华冠 HGSEMI/HG24C08.pdf 648.67KB
广东华冠 HGSEMI/HG24C1024.iic 5.33KB
广东华冠 HGSEMI/HG24C1024.pdf 615.06KB
广东华冠 HGSEMI/HG24C128.iic 5.33KB
广东华冠 HGSEMI/HG24C128.pdf 721.85KB
广东华冠 HGSEMI/HG24C16.iic 5.33KB
广东华冠 HGSEMI/HG24C16.pdf 648.67KB
广东华冠 HGSEMI/HG24C256.iic 5.33KB
广东华冠 HGSEMI/HG24C256.pdf 721.85KB
广东华冠 HGSEMI/HG24C256C.iic 5.33KB
广东华冠 HGSEMI/HG24C256C.pdf 3.39MB
广东华冠 HGSEMI/HG24C32.iic 5.33KB
广东华冠 HGSEMI/HG24C32.pdf 607.03KB
广东华冠 HGSEMI/HG24C512.iic 5.33KB
广东华冠 HGSEMI/HG24C512.pdf 574.4KB
广东华冠 HGSEMI/HG24C64.iic 5.33KB
广东华冠 HGSEMI/HG24C64.pdf 607.03KB
广东华冠 HGSEMI/HG24LC128.iic 5.33KB
广东华冠 HGSEMI/HG24LC128.pdf 618.6KB
广东华冠 HGSEMI/HG24LC256.iic 5.33KB
广东华冠 HGSEMI/HG24LC256.pdf 618.6KB
广东华冠 HGSEMI/手机淘宝APP扫码.png 16.8KB