ppt高效制作技巧与方法

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ppt高效制作技巧与方法

www.latticesemi.com 1 rd1174_01.1

March 2014 Reference Design RD1174

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Introduction

The Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that

has a synchronous interface. SDR (Single Data Rate) SDRAM can accept one command and transfer one word of

data per clock cycle. Typical SDR SDRAM clock rates are 66, 100, and 133 MHz (periods of 15, 10, and 7.5 ns). It

is a mainstream memory of choice due to speed, burst access and pipeline features.

This SDRAM Controller reference design, located between the SDRAM and the bus master, reduces the user’s

effort to deal with the SDRAM command interface by providing a simple generic system interface to the bus master.

The design is implemented in Verilog language. The Lattice Diamond

for MachXO3L device and Lattice

iCEcube2™ for iCE40™ device Place and Route tool integrated with the Synopsys Synplify Pro

synthesis tool are

used for the implementation of the design. The design can be targeted to other iCE40 FPGA product family

devices.

Features

• Supports up to 27 address space, up to 4 banks

• Compile time configurable timing parameters like (CAS latency, tRP, tRCD, tREFC, tMRD …)

• Simplifies SDRAM command interface to standard system read/write interface

• Supports Auto Refresh and Self Refresh

• Supports flexible Row and Column addressing

• Supports CAS latencies of 2 and 3

• Run time configurable Refresh rate

• Automatically generates initialization and refresh sequences

• Flexible user controlled burst length of 1, 2, 4, 8 and page as well as stop signal

• User friendly control and status signals like busy, command acknowledge, data valid and request, indications for

completion of write and read data

• User controlled operation modes by configuring load mode register

• Provision for disable auto refresh

• Power down mode

SDR SDRAM Controller

System Block Diagram

Figure 1. System Block Diagram

Functional Description

Figure 2. Functional Block Diagram

IOB

SDR SDRAM

Controller

Processor

i_clk

i_rst

CONTROL

STATUS

ADDRESS

i_data

o_data

SDR SD

Memory

Device

o_sdram_clk

COMMAND

ADDRESS

i_sdram_dat

_sdram_data

Autorefresh

Counter

100 us delay

generator

Initialization

FSM

Command

Generation

FSM

Status

Signals

Generation

Control

Logic

Module

SDR SDRAM

i_clk

i_rst

CONTROL

STATUS

ADDRESS

i_data

o_data

o_sdram_clk

COMMAND

ADDRESS

i_sdram_data

o_sdram_data

SDR SDRAM Controller

Design Details

Initialization

Prior to performing normal SDRAM memory access, memory needs to be initialized by a sequence of commands.

Operational procedures other than those specified may result in undefined operation. The Initialization FSM han-

dles this initialization.

Figure 3. SDRAM Initialization flow chart

Command Generation

Commands are generated in command generation FSM. Table 1 shows Truth table for various commands and cor-

responding SDR SDRAM control signal levels.

Table 1. Truth Table for SDRAM Commands

Command generation FSM states and its control signals are shown in Figure 4.

Commands CS RAS CAS WE

No Operation (NOP) LHHH

Active L L H H

Read LHLH

Write L H L L

Burst Terminate L H H L

Precharge L L H L

Auto Refresh or Self Refresh L L L H

IDLE STATE

Wait for 100 us

Precharge all the banks

Wait for Precharge Period- tRP

Issue first Auto Reresh Command

Wait for Auto Refresh Period -tRFC

Issue Second Auto Refresh Command

Wait for Au to Refresh Period - tRFC

Load Mode Register

Wait for Load Mode Register Delay-

tMRD

Initialization Done

SDR SDRAM Controller

Figure 4. Command Generation FSM

Command Generation FSM will generate SDR SDRAM commands.

Read and Write access to the SDRAM are burst oriented, accesses starts at a specified address and continue for

a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE

command, which is then followed by a READ or WRITE command. The address bits coincident with the ACTIVE

command are used to select the bank and row to be accessed. The address bits coincident with the READ or

WRITE command are used to select the starting column location for the burst access.

The controller provides programmable READ or WRITE burst lengths 1, 2, 4 or 8 locations, or the full page, with a

burst terminate option. An auto precharge function may be enabled to provide a row precharge that is initiated at

the end of the burst sequence.

IDLE

SELF

REFRESH

AUTO

REFRESH

LOAD MODE

REG

PRECHARGE

i_selfrefresh_req

i_refresh_req

i_loadmod_req

i_precharge_req

! (i_cpu_advn) &&

o_init_done

ACTIVE

DONE_ACTIVE2RW_DE

LAY && i_cpu_rwn = 1

READ AUTO

PRECHARGE

WRITE AUTO

PRECHARGE

DONE_ACTIVE2RW_D

ELAY && i_cpu_rwn = 0

CAS LATENCY

READ DATA

DONE_CAS_LATENCY

BURST STOP

READ

WRITE DATA

i_burststop_req

BURST STOP

WRITE

DONE_READ_BURST

DATAIN2ACTIVE

DONE_WRITE_BURST

DONE_DATAIN2ACTIVE

DONE_AUTOREFRESH_PERIOD

DONE_SELFREFRESH

2ACTIVE_DELAY

DONE_LOAD_MO

DEREG_DELAY

DONE_CAS_LATENCY

DONE_WRITE_

RECOVERY_DELAY

DONE_PRECHARGE_PERIOD

SDR SDRAM Controller

Signal Description

Table 2. Signal Description

Initialization Conditions

An asynchronous active low reset signal assertion is necessary to initialize the SDR SDAM Controller to proper

operating state.

Signal Width Type Description

i_clk 1 Input System Clock

i_rst 1 Input Asynchronous Active low Reset

i_advn 1 Input Active low Address enable for Active state

i_rwn 1 Input R/W Enable: 1-Read,0-Write

i_addr [ROWADDR_MSB:COLADDR_LS

Input

Input Address to SDRAM Controller

i_selfrefrresh_req 1 Input Request for Self Refresh

i_loadmod_req 1 Input Request for Loading Mode Register

i_burststop_req 1 Input Request for Burst Stop

i_disable_active 1 Input Disables opening a row if already opened

i_disable_precharge 1 Input Disables precharge, keep open for next R/W

i_precharge_req 1 Input Request for precharge

i_data [CPU_DATA_WIDTH-1:0] Input Input data to the SDRAM Controller

i_power_down 1 Input Enables power down mode if high

i_disable_autorefresh 1 Input Disables auto refresh

o_data [CPU_DATA_WIDTH-1:0] Output Output data from the SDRAM Controller

o_write_done

1 Output

When High, indicates that write to SDRAM is com-

plete

o_read_done

1 Output

When High, indicates that read from SDRAM is

complete

o_data_valid

1 Output

Output data valid, can be used for FIFO Write

Enable

o_data_req

1 Output

Input data request, can be used for FIFO read

Enable

o_busy

1 Output

Active low busy signal which indicates SDRAM

Controller is busy

o_init_done 1 Output Indicates Initialization of SDRAM is completed

o_ack

1 Output

Indicates controller is about to start write, read, or

load mode register operation

o_sdram_addr [SDRAM_ADDR_WIDTH-1:0] Output SDRAM address

o_sdram_blkaddr [SDRAM_BLKADR_WIDTH-1:0] Output SDRAM Bank Address

o_sdram_casn 1 Output SDRAM column select

o_sdram_cke 1 Output SDRAM Clock Enable

o_sdram_csn 1 Output SDRAM Chip Select

o_sdram_dqm [SDRAM_DQM_WIDTH-1:0] Output SDRAM Data Mask

o_sdram_rasn 1 Output SDRAM row address select

o_sdram_wen 1 Output SDRAM write enable

o_sdram_clk 1 Output SDRAM clock

i_sdram_dq [SDRAM_DATA_WIDTH-1:0] Input SDRAM input data

o_sdram_dq [SDRAM_DATA_WIDTH-1:0] Output SDRAM output data

资源文件列表:

Documents.zip 大约有4个文件

sdrsdramcontroller-sourcecode.zip 2.58MB
sdrsdramcontroller-documentation.pdf 1.41MB
fpga-rd-02087-4-9-advanced-sdr-sdram-controller-design-documentation.pdf 1.14MB
advancedsdrsdramcontroller-sourcecode.zip 495.7KB