APM32E103系列单片机工程的创建(仿江科大工程)

/*! * @file apm32e10x_tmr.c * * @brief This file provides all the TMR firmware functions. * * @version V1.0.2 * * @date 2022-12-31 * * @attention * * Copyright (C) 2021-2023 Geehy Semiconductor * * You may not use this file except in compliance with the * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions * and limitations under the License. */ #include "apm32e10x_tmr.h" #include "apm32e10x_rcm.h" /** @addtogroup APM32E10x_StdPeriphDriver @{ */ /** @addtogroup TMR_Driver * @brief TMR driver modules @{ */ /** @defgroup TMR_Functions Functions @{ */ static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); /*! * @brief Deinitializes the TMRx peripheral registers to their default reset values. * * @param tmr: Select TMRx peripheral, The x can be 1 to 8 * * @retval None * * @note */ void TMR_Reset(TMR_T* tmr) { if (tmr == TMR1) { RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_TMR1); RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_TMR1); } else if (tmr == TMR2) { RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR2); RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR2); } else if (tmr == TMR3) { RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR3); RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR3); } else if (tmr == TMR4) { RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR4); RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR4); } else if (tmr == TMR5) { RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR5); RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR5); } else if (tmr == TMR6) { RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR6); RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR6); } else if (tmr == TMR7) { RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR7); RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR7); } else if (tmr == TMR8) { RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_TMR8); RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_TMR8); } } /*! * @brief Initializes the base timer through the structure * * @param tmr: Select TMRx peripheral, The x can be 1 to 8 * * @param baseConfig: Pointer to a TMR_BaseConfig_T structure * * @retval None */ void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig) { uint16_t temp; if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) || (tmr == TMR4) || (tmr == TMR5)) { temp = tmr->CTRL1; temp &= 0x038F; temp |= baseConfig->countMode; tmr->CTRL1 = temp; } if ((tmr != TMR6) && (tmr != TMR7)) { tmr->CTRL1_B.CLKDIV = baseConfig->clockDivision; } tmr->AUTORLD = baseConfig->period; tmr->PSC = baseConfig->division; if ((tmr == TMR1) || (tmr == TMR8)) { tmr->REPCNT = baseConfig->repetitionCounter; } tmr->CEG_B.UEG = 0x01; } /*! * @brief Configure channel 1 according to parameters * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * * @param OC1Config: Pointer to a TMR_OCConfig_T structure * * @retval None */ void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OC1Config) { tmr->CCEN_B.CC1EN = BIT_RESET; tmr->CCM1_COMPARE_B.CC1SEL = BIT_RESET; tmr->CCM1_COMPARE_B.OC1MOD = OC1Config->mode; tmr->CCEN_B.CC1POL = OC1Config->polarity; tmr->CCEN_B.CC1EN = OC1Config->outputState; if ((tmr == TMR1) || (tmr == TMR8)) { tmr->CCEN_B.CC1NPOL = OC1Config->nPolarity; tmr->CCEN_B.CC1NEN = OC1Config->outputNState; tmr->CTRL2_B.OC1OIS = BIT_RESET; tmr->CTRL2_B.OC1NOIS = BIT_RESET; tmr->CTRL2_B.OC1OIS = OC1Config->idleState; tmr->CTRL2_B.OC1NOIS = OC1Config->nIdleState; } tmr->CC1 = OC1Config->pulse; } /*! * @brief Configure channel 2 according to parameters * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * * @param OC2Config: Pointer to a TMR_OCConfig_T structure * * @retval None */ void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OC2Config) { tmr->CCEN_B.CC2EN = BIT_RESET; tmr->CCM1_COMPARE_B.OC2MOD = BIT_RESET; tmr->CCM1_COMPARE_B.CC2SEL = BIT_RESET; tmr->CCM1_COMPARE_B.OC2MOD = OC2Config->mode; tmr->CCEN_B.CC2POL = BIT_RESET; tmr->CCEN_B.CC2POL = OC2Config->polarity; tmr->CCEN_B.CC2EN = OC2Config->outputState; if ((tmr == TMR1) || (tmr == TMR8)) { tmr->CCEN_B.CC2NPOL = BIT_RESET; tmr->CCEN_B.CC2NPOL = OC2Config->nPolarity; tmr->CCEN_B.CC2NEN = BIT_RESET; tmr->CCEN_B.CC2NEN = OC2Config->outputNState; tmr->CTRL2_B.OC2OIS = BIT_RESET; tmr->CTRL2_B.OC2NOIS = BIT_RESET; tmr->CTRL2_B.OC2OIS = OC2Config->idleState; tmr->CTRL2_B.OC2NOIS = OC2Config->nIdleState; } tmr->CC2 = OC2Config->pulse; } /*! * @brief Configure channel 3 according to parameters * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * * @param OC3Config: Pointer to a TMR_OCConfig_T structure * * @retval None */ void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OC3Config) { tmr->CCEN_B.CC3EN = BIT_RESET; tmr->CCM2_COMPARE_B.OC3MOD = BIT_RESET; tmr->CCM2_COMPARE_B.CC3SEL = BIT_RESET; tmr->CCM2_COMPARE_B.OC3MOD = OC3Config->mode; tmr->CCEN_B.CC3POL = BIT_RESET; tmr->CCEN_B.CC3POL = OC3Config->polarity; tmr->CCEN_B.CC3EN = OC3Config->outputState; if ((tmr == TMR1) || (tmr == TMR8)) { tmr->CCEN_B.CC3NPOL = BIT_RESET; tmr->CCEN_B.CC3NPOL = OC3Config->nPolarity; tmr->CCEN_B.CC3NEN = BIT_RESET; tmr->CCEN_B.CC3NEN = OC3Config->outputNState; tmr->CTRL2_B.OC3OIS = BIT_RESET; tmr->CTRL2_B.OC3NOIS = BIT_RESET; tmr->CTRL2_B.OC3OIS = OC3Config->idleState; tmr->CTRL2_B.OC3NOIS = OC3Config->nIdleState; } tmr->CC3 = OC3Config->pulse; } /*! * @brief Configure channel 4 according to parameters * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * * @param OC4Config: Pointer to a TMR_OCConfig_T structure * * @retval None */ void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OC4Config) { tmr->CCEN_B.CC4EN = BIT_RESET; tmr->CCM2_COMPARE_B.OC4MOD = BIT_RESET; tmr->CCM2_COMPARE_B.CC4SEL = BIT_RESET; tmr->CCM2_COMPARE_B.OC4MOD = OC4Config->mode; tmr->CCEN_B.CC4POL = BIT_RESET; tmr->CCEN_B.CC4POL = OC4Config->polarity; tmr->CCEN_B.CC4EN = OC4Config->outputState; if ((tmr == TMR1) || (tmr == TMR8)) { tmr->CTRL2_B.OC4OIS = BIT_RESET; tmr->CTRL2_B.OC4OIS = OC4Config->idleState; } tmr->CC4 = OC4Config->pulse; } /*! * @brief Configure Peripheral equipment * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * * @param ICConfig: Pointer to a TMR_ICConfig_T structure * * @retval None */ void TMR_ConfigIC(TMR