ST7701
Preliminary Version 1.0 Page 3 of 305 2015/10
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disclosed in whole or in part without prior written permission of Sitronix.
8.2.1.1
Command write mode .......................................................................................................................... 59
8.2.2
Read function ............................................................................................................................................ 61
8.3
16
BIT
S
ERIAL
I
NTERFACE
............................................................................................................................... 65
8.3.1
Write Mode ................................................................................................................................................ 65
8.3.2
Read Mode ................................................................................................................................................ 67
8.4
I
2
C
SERIAL
I
NTERFACE
.................................................................................................................................... 69
8.4.1
Characteristics of I
2
C bus ......................................................................................................................... 69
8.4.1.1
System configuration ............................................................................................................................ 69
8.4.1.2
Bit transfer ........................................................................................................................................... 69
8.4.1.3
START and STOP conditions ................................................................................................................ 70
8.4.1.4
Acknowledgment .................................................................................................................................. 70
8.4.1.5
I
2
C bus protocol ................................................................................................................................... 71
8.4.1.6
I2C bus Write Instruction and parameter ............................................................................................. 71
8.4.1.7
I2C bus read ......................................................................................................................................... 71
8.5
D
ATA
T
RANSFER
B
REAK AND
R
ECOVERY
....................................................................................................... 72
8.6
D
ATA
T
RANSFER
P
AUSE
.................................................................................................................................. 74
8.6.1
SPI interface pause ................................................................................................................................... 75
8.7
RGB
I
NTERFACE
............................................................................................................................................. 76
8.7.1
RGB Color Format ................................................................................................................................... 77
8.7.2
RGB Interface Definition .......................................................................................................................... 78
8.7.3
RGB Interface Mode Selection .................................................................................................................. 79
8.7.4
RGB Interface Timing ............................................................................................................................... 79
8.8
MIPI-DSI
INTERFACE
..................................................................................................................................... 81
8.8.1
Display Module Pin Configuration for DSI .............................................................................................. 82
8.8.2
Display Serial Interface (DSI) .................................................................................................................. 83
8.8.2.1
General description .............................................................................................................................. 83
8.8.2.2
Interface level communication ............................................................................................................. 83
8.8.2.2.1
General ................................................................................................................................................ 83
8.8.2.2.2
DSI-CLK Lanes .................................................................................................................................... 85
8.8.2.2.2.1
Low Power Mode (LPM) ................................................................................................................. 86
8.8.2.2.2.2
Ultra Low Power Mode (ULPM) .................................................................................................... 88
8.8.2.2.2.3
High-speed Clock Mode (HSCM) .................................................................................................... 89
8.8.2.2.3
DSI-DATA LANES ................................................................................................................................ 91
8.8.2.2.3.1
GENERAL ....................................................................................................................................... 91
8.8.2.2.3.2
ESCAPE MODE .............................................................................................................................. 92
8.8.2.2.3.3
HIGH SPEED DATA TRANSMISSION (HSDT) .............................................................................. 99
8.8.2.3
Packet Level Communication ............................................................................................................. 104
8.8.2.3.1
Short Packet (SPA) And Long Packet (LPA) Structure ....................................................................... 104