ds180-7Series-Overview.pdf

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ds180_7Series_Overview.pdf

DS180 (v1.13) November 30, 2012 www.xilinx.com

Advance Product Specification 1

United States and other countries. PCI Express is a trademark of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

General Description

Xilinx® 7 series FPGAs comprise three new FPGA families that address the complete range of system requirements, ranging from low cost, small form

factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most

demanding high-performance applications. The 7 series devices are the programmable silicon foundation for Targeted Design Platforms that enable

designers to focus on innovation from the outset of their development cycle. The 7 series FPGAs include:

• Artix™-7 Family: Optimized for lowest cost and power with small

form-factor packaging for the highest volume applications.

• Kintex™-7 Family: Optimized for best price-performance with a 2X

improvement compared to previous generation, enabling a new class

of FPGAs.

• Virtex®-7 Family: Optimized for highest system performance and

capacity with a 2X improvement in system performance. Highest

capability devices enabled by stacked silicon interconnect (SSI)

technology.

Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an

unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less

power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs. All 7 series devices share a scalable, optimized

fourth-generation Advanced Silicon Modular Block (ASMBL™) column-based architecture that reduces system development and deployment time with

simplified design portability.

Summary of 7 Series FPGA Features

• Advanced high-performance FPGA logic based on real 6-input look-

up table (LUT) technology configurable as distributed memory.

• 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data

buffering.

• High-performance SelectIO™ technology with support for DDR3

interfaces up to 1,866 Mb/s.

• High-speed serial connectivity with built-in multi-gigabit transceivers

from 600 Mb/s to maximum rates of 6.6 Gb/s up to 28.05 Gb/s,

offering a special low-power mode, optimized for chip-to-chip

interfaces.

• A user configurable analog interface (XADC), incorporating dual

12-bit 1MSPS analog-to-digital converters with on-chip thermal and

supply sensors.

• DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder

for high performance filtering, including optimized symmetric

coefficient filtering.

• Powerful clock management tiles (CMT), combining phase-locked

loop (PLL) and mixed-mode clock manager (MMCM) blocks for high

precision and low jitter.

• Integrated block for PCI Express® (PCIe), for up to x8 Gen3

Endpoint and Root Port designs.

• Wide variety of configuration options, including support for

commodity memories, 256-bit AES encryption with HMAC/SHA-256

authentication, and built-in SEU detection and correction.

• Low-cost, wire-bond, lidless flip-chip, and high signal integrity flip-

chip packaging offering easy migration between family members in

the same package. All packages available in Pb-free and selected

packages in Pb option.

• Designed for high performance and lowest power with 28 nm,

HKMG, HPL process, 1.0V core voltage process technology and

0.9V core voltage option for even lower power.

7 Series FPGAs Overview

DS180 (v1.13) November 30, 2012 Advance Product Specification

Table 1: 7 Series Families Comparison

Maximum Capability Artix-7 Family Kintex-7 Family Virtex-7 Family

Logic Cells 215K 478K 1,955K

Block RAM

(1)

13 Mb 34 Mb 68 Mb

DSP Slices 740 1,920 3,600

Peak DSP Performance

(2)

929 GMAC/s 2,845 GMAC/s 5,335 GMAC/s

Transceivers 16 32 96

Peak Transceiver Speed 6.6 Gb/s 12.5 Gb/s 28.05 Gb/s

Peak Serial Bandwidth (Full Duplex) 211 Gb/s 800 Gb/s 2,784 Gb/s

PCIe Interface x4 Gen2 x8 Gen2 x8 Gen3

Memory Interface 1,066 Mb/s 1,866 Mb/s 1,866 Mb/s

I/O Pins 500 500 1,200

I/O Voltage 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V

Package Options Low-Cost, Wire-Bond, Lidless

Flip-Chip

Low-Cost, Lidless Flip-Chip and

High-Performance Flip-Chip

Highest Performance Flip-Chip

Notes:

1. Additional memory available in the form of distributed RAM.

2. Peak DSP performance numbers are based on symmetrical filter implementation.

7 Series FPGAs Overview

DS180 (v1.13) November 30, 2012 www.xilinx.com

Advance Product Specification 2

Artix-7 FPGA Feature Summary

Table 2: Artix-7 FPGA Feature Summary by Device

Device

Logic

Cells

Configurable Logic Blocks

(CLBs)

DSP48E1

Slices

(2)

Block RAM Blocks

(3)

Clock Mgmt

Tiles

(CMTs)

(4)

PCIe

(5)

GTPs

XADC

Blocks

(6)

Total I/O

Banks

(7)

Max

User

I/O

(8)

Slices

(1)

Max

Distributed

RAM (Kb)

18Kb 36Kb

Max

(Kb)

XC7A20SL 16,000 2,500 208 60 60 30 1,080 3 0 0 1 5 216

XC7A35SL 32,909 5,142 453 120 130 65 2,340 3 0 0 1 5 216

XC7A50SL 52,480 8,200 688 180 190 95 3,420 4 0 0 1 6 300

XC7A75SL 71,642 11,194 974 240 250 125 4,500 4 0 0 1 6 300

XC7A20SLT 16,000 2,500 208 60 60 30 1,080 3 1 4 1 5 216

XC7A35SLT 32,909 5,142 453 120 130 65 2,340 3 1 4 1 5 216

XC7A50SLT 52,480 8,200 688 180 190 95 3,420 4 1 8 1 6 300

XC7A75SLT 71,642 11,194 974 240 250 125 4,500 4 1 8 1 6 300

XC7A100T 101,440 15,850 1,188 240 270 135 4,860 6 1 8 1 6 300

XC7A200T 215,360 33,650 2,888 740 730 365 13,140 10 1 16 1 10 500

Notes:

1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.

2. Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.

3. Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb blocks.

4. Each CMT contains one MMCM and one PLL.

5. Artix-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.

6. Artix-7 SL/SLT devices have enhanced analog functionality.

7. Does not include configuration Bank 0.

8. This number does not include GTP, GTX, or GTH transceivers.

Table 3: Artix-7 FPGA Device-Package Combinations and Maximum I/Os

Package

(1)

CPG236 CSG325 CSG484 CPG237 CSG326 CSG485 FGG677

Size (mm) 10 x 10 15 x 15 19 x 19 10 x 10 15 x 15 19 x 19 27 x 27

Ball Pitch (mm) 0.5 0.8 0.8 0.5 0.8 0.8 1.0

Device GTP

I/O

GTP

I/O

GTP

I/O

GTP

I/O

GTP

I/O

GTP

I/O

GTP

I/O

(2)

(3)

(2)

(3)

(2)

(3)

(2)

(3)

(2)

(3)

(2)

(3)

(2)

(3)

XC7A20SL 0 48 52 0 108 108

XC7A35SL 0 48 52 0 108 108

XC7A50SL 0 144 156

XC7A75SL 0 144 156

XC7A20SLT 1 48 52 4 108 77 4 108 108

XC7A35SLT 1 48 52 4 108 77 4 108 108

XC7A50SLT 4 108 77 6 126 108 8 144 156

XC7A75SLT

4 108 77 6 126 108 8 144 156

Notes:

1. All packages listed in this table are Pb-free.

2. HR = High Range I/O with support for I/O voltage from 1.2V to 3.3V.

3. HD = High Density I/O.

7 Series FPGAs Overview

DS180 (v1.13) November 30, 2012 www.xilinx.com

Advance Product Specification 3

Kintex-7 FPGA Feature Summary

Table 4: Artix-7 FPGA Device-Package Combinations and Maximum I/Os - Continued

Package

(1)

CSG324 FTG256 SBG484 FGG484

(2)

FBG484

(2)

FGG676

(3)

FBG676

(3)

FFG1156

Size (mm) 15 x 15 17 x 17 19 x 19 23 x 23 23 x 23 27 x 27 27 x 27 35 x 35

Ball Pitch (mm) 0.8 1.0 0.8 1.0 1.0 1.0 1.0 1.0

Device GTP

I/O

GTP

I/O

GTP

I/O

GTP

I/O

GTP

I/O

GTP

I/O

GTP

I/O

GTP

I/O

(4)

XC7A100T 0 210 0 170 4 285 8300

XC7A200T 4 285 4285 8 400 16 500

Notes:

1. All packages listed are Pb-free. Some packages are available in Pb option.

2. Devices in FGG484 and FBG484 are footprint compatible.

3. Devices in FGG676 and FBG676 are footprint compatible.

4. HR = High Range I/O with support for I/O voltage from 1.2V to 3.3V.

Table 5: Kintex-7 FPGA Feature Summary by Device

Device

Logic

Cells

Configurable Logic

Blocks (CLBs)

DSP

Slices

(2)

Block RAM Blocks

(3)

CMTs

(4)

PCIe

(5)

GTXs

XADC

Blocks

Total I/O

Banks

(6)

Max

User

I/O

(7)

Slices

(1)

Max

Distributed

RAM (Kb)

18 Kb 36 Kb Max (Kb)

XC7K70T 65,600 10,250 838 240 270 135 4,860 6 1 8 1 6 300

XC7K160T 162,240 25,350 2,188 600 650 325 11,700 8 1 8 1 8 400

XC7K325T 326,080 50,950 4,000 840 890 445 16,020 10 1 16 1 10 500

XC7K355T 356,160 55,650 5,088 1,440 1,430 715 25,740 6 1 24 1 6 300

XC7K410T 406,720 63,550 5,663 1,540 1,590 795 28,620 10 1 16 1 10 500

XC7K420T 416,960 65,150 5,938 1,680 1,670 835 30,060 8 1 32 1 8 400

XC7K480T 477,760 74,650 6,788 1,920 1,910 955 34,380 8 1 32 1 8 400

Notes:

1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.

2. Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.

3. Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb blocks.

4. Each CMT contains one MMCM and one PLL.

5. Kintex-7 FPGA Interface Blocks for PCI Express support up to x8 Gen 2.

6. Does not include configuration Bank 0.

7. This number does not include GTP, GTX, or GTH transceivers.

7 Series FPGAs Overview

DS180 (v1.13) November 30, 2012 www.xilinx.com

Advance Product Specification 4

Virtex-7 FPGA Feature Summary

Table 6: Kintex-7 FPGA Device-Package Combinations and Maximum I/Os

Package

(1)

FBG484 FBG676

(2)

FFG676

(2)

FBG900

(3)

FFG900

(3)

FFG901 FFG1156

Size (mm) 23 x 23 27 x 27 27 x 27 31 x 31 31 x 31 31 x 31 35 x 35

Ball Pitch

(mm)

1.0 1.0 1.0 1.0 1.0 1.0 1.0

Device GTX

I/O

GTX

I/O

GTX

I/O

GTX

I/O

GTX

I/O

GTX

I/O

GTX

I/O

(4)

(5)

(4)

(5)

(4)

(5)

(4)

(5)

(4)

(5)

(4)

(5)

(4)

(5)

XC7K70T 4 185 100 8 200 100

XC7K160T 4 185 100 8 250 150 8 250 150

XC7K325T 8 250 150 8 250 150 16 350 150 16 350 150

XC7K355T 24 300 0

XC7K410T 8 250 150 8 250 150 16 350 150 16 350 150

XC7K420T 28 380 0 32 400 0

XC7K480T

28 380 0 32 400 0

Notes:

1. All packages listed are Pb-free. Some packages are available in Pb option.

2. Devices in FBG676 and FFG676 are footprint compatible.

3. Devices in FBG900 and FFG900 are footprint compatible.

4. HR = High Range I/O with support for I/O voltage from 1.2V to 3.3V.

5. HP = High Performance I/O with support for I/O voltage from 1.2V to 1.8V.

Table 7: Virtex-7 FPGA Feature Summary

Device

(1)

Logic

Cells

Configurable Logic

Blocks (CLBs)

DSP

Slices

(3)

Block RAM Blocks

(4)

CMTs

(5)

PCIe

(6)

GTX GTH GTZ

XADC

Blocks

Total I/O

Banks

(7)

Max

User

I/O

(8)

SLRs

(9)

Slices

(2)

Max

Distributed

RAM (Kb)

18 Kb 36 Kb

Max

(Kb)

XC7V585T 582,720 91,050 6,938 1,260 1,590 795 28,620 18 3 36 0 0 1 17 850 N/A

XC7V2000T 1,954,560 305,400 21,550 2,160 2,584 1,292 46,512 24 4 36 0 0 1 24 1,200 4

XC7VX330T 326,400 51,000 4,388 1,120 1,500 750 27,000 14 2 0 28 0 1 14 700 N/A

XC7VX415T 412,160 64,400 6,525 2,160 1,760 880 31,680 12 2 0 48 0 1 12 600 N/A

XC7VX485T 485,760 75,900 8,175 2,800 2,060 1,030 37,080 14 4 56 0 0 1 14 700 N/A

XC7VX550T 554,240 86,600 8,725 2,880 2,360 1,180 42,480 20 2 0 80 0 1 16 600 N/A

XC7VX690T 693,120 108,300 10,888 3,600 2,940 1,470 52,920 20 3 0 80 0 1 20 1,000 N/A

XC7VX980T 979,200 153,000 13,838 3,600 3,000 1,500 54,000 18 3 0 72 0 1 18 880 N/A

XC7VX1140T 1,139,200 178,000 17,700 3,360 3,760 1,880 67,680 24 4 0 96 0 1 22 1,100 4

XC7VH580T 580,480 90,700 8,850 1,680 1,880 940 33,840 12 2 0 48 8 1 12 600 2

XC7VH870T 876,160 136,900 13,275 2,520 2,820 1,410 50,760 18 3 0 72 16 1 13 650 3

Notes:

1. EasyPath™-7 FPGAs are also available to provide a fast, simple, and risk-free solution for cost reducing Virtex-7 T and Virtex-7 XT FPGA designs

2. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.

3. Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.

4. Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb blocks.

5. Each CMT contains one MMCM and one PLL.

6. Virtex-7 T FPGA Interface Blocks for PCI Express support up to x8 Gen 2. Virtex-7 XT and Virtex-7 HT Interface Blocks for PCI Express support up to x8 Gen 3, with the

exception of the XC7VX485T device, which supports x8 Gen 2.

7. Does not include configuration Bank 0.

8. This number does not include GTP, GTX, GTH, or GTZ transceivers.

9. Super logic regions (SLRs) are the constituent parts of FPGAs that use SSI technology. Virtex-7 HT devices use SSI technology to connect SLRs with 28.05 Gb/s

transceivers.

7 Series FPGAs Overview

DS180 (v1.13) November 30, 2012 www.xilinx.com

Advance Product Specification 5

Table 8: Virtex-7 FPGA Device-Package Combinations and Maximum I/Os

Package

(1)

FFG1157 FFG1761

(2)

FHG1761

(2)

FLG1925

Size (mm) 35 x 35 42.5 x 42.5 45 x 45 45 x 45

Ball Pitch 1.0 1.0 1.0 1.0

Device

GTX

GTH

I/O

GTX GTH

I/O

GTX GTH

I/O

GTX

I/O

(3)

(4)

(3)

(4)

(3)

(4)

(3)

(4)

XC7V585T 20 0 0 600 36 0 100 750

XC7V2000T 36 0 0 850 16 0 1,200

XC7VX330T 0 20 0 600 0 28 50 650

XC7VX415T 0 20 0 600

XC7VX485T 20 0 0 600 28 0 0 700

XC7VX550T

XC7VX690T 0 20 0 600 0 36 0 850

XC7VX980T

XC7VX1140T

Notes:

1. All packages listed are Pb-free. Some packages are available in Pb option.

2. Devices in FFG1761 and FHG1761 are footprint compatible.

3. HR = High Range I/O with support for I/O voltage from 1.2V to 3.3V.

4. HP = High Performance I/O with support for I/O voltage from 1.2V to 1.8V.

Table 9: Virtex-7 FPGA Device-Package Combinations and Maximum I/Os - Continued

Package

(1)

FFG1158 FFG1926

(2)

FLG1926

(2)

FFG1927 FFG1928

(3)

FLG1928

(3)

FFG1930

(4)

FLG1930

(4)

Size (mm) 35 x 35 45 x 45 45 x 45 45 x 45 45 x 45 45 x 45 45 x 45 45 x 45

Ball Pitch 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0

Device GTX GTH

I/O

GTX GTH

I/O

GTX GTH

I/O

GTX GTH

I/O

GTX GTH

I/O

GTX GTH

I/O

GTX GTH

I/O

GTX GTH

I/O

(5)

XC7V585T

XC7V2000T

XC7VX330T

XC7VX415T 0 48 350 048600

XC7VX485T 48 0 350 56 0 600 24 0 700

XC7VX550T 0 48 350 080600

XC7VX690T 0 48 350 0 64 720 080600 0 24 1,000

XC7VX980T 064720 072480 024900

XC7VX1140T 064720 0 96 480 0 24 1,100

Notes:

1. All packages listed are Pb-free. Some packages are available in Pb option.

2. Devices in FFG1926 and FLG1926 are footprint compatible.

3. Devices in FFG1928 and FLG1928 are footprint compatible.

4. Devices in FFG1930 and FLG1930 are footprint compatible.

5. HP = High Performance I/O with support for I/O voltage from 1.2V to 1.8V.

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