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ug472-7Series-Clocking.pdf

7 Series FPGAs

Clocking Resources

User Guide

UG472 (v1.14) July 30, 2018

7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.14) July 30, 2018

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UG472 (v1.14) July 30, 2018 www.xilinx.com 7 Series FPGAs Clocking Resources User Guide

Revision History

The following table shows the revision history for this document.

Date Version Revision

03/01/2011 1.0 Initial Xilinx release.

03/28/2011 1.1 Updated disclaimer and copyright on page 2. Updated Clocking Architecture Overview

and Figure 2-2. Revised the discussion in Clock-Capable Inputs including adding

Table 1-1 and Figure 2-1. Revised some of the Global Clock Buffers descriptions. Revised

the description under Figure 2-17. Updated the I/O Clock Buffer—BUFIO section.

Updated Figure 2-20. Updated the Regional Clock Buffer—BUFR section. Updated the

description in Table 2-8. Revised Figure 2-23. Added the BUFMRCE to the BUFMR

Primitive section including Figure 2-25. Added BUFHCE to the Horizontal Clock

Buffer—BUFH, BUFHCE section. Moved Clock Gating for Power Savings.

Updated the MMCMs and PLLs section. Revised the Frequency Synthesis Only Using

Integer Divide section including Figure 3-4. Revised the discussion around adjacent

regions in CLKOUT[0:6] – Output Clocks. Updated the examples after Equation 3-11.

Moved and revised VHDL and Verilog Templates and the Clocking Wizard.

Added Appendix A, Multi-Region Clocking.

05/31/2011 1.2 Added section on 7 Series FPGAs Clocking Differences from Previous FPGA

Generations.

Updated Figure 2-2. Clarified discussion in Clock-Capable Inputs section including

removing Table 1-1: Migration of devices in the same package with different top/bottom

alignments. Redrew Figure 2-4, Figure 2-16, Figure 2-18, and Figure 2-22.

Updated description of CLKOUT[0:6] in Table 3-5. Updated CLKFBSTOPPED –

Feedback Clock Status, page 83. Clarified the MMCM/PLL relationship including

updating Figure 3-10. Added more information to the Phase Shift section, including

Equation 3-5.

Revised Figure A-6 and

Figure A-7. Added Appendix B, Clocking Resources and

Connectivity Variations per Clock Region.

10/27/2011 1.3 Moved 7 Series FPGAs Clocking Differences from Previous FPGA Generations. Added

Clock Buffer Selection Considerations. Clarified description in Clock-Capable Inputs.

Added another note after Figure 2-22, page 53. Added the Stacked Silicon Interconnect

Clocking section.

Updated Figure 3-6, page 73. Clarified descriptions in Frequency Synthesis Using

Fractional Divide in the MMCM, page 73, Interpolated Fine Phase Shift in Fixed or

Dynamic Mode in the MMCM, page 75, Determine the Input Frequency, page 76,

CLKOUT[0:6] – Output Clocks, page 82, and Reference Clock Switching, page 91.

Revised description of STARTUP_WAIT, page 85. Updated RST description in Table 3-5,

page 78. Updated CLKOUT[0]_DIVIDE_F(2) allowed values in Table 3-7, page 83.

Updated Clock Network Deskew, page 72 adding Figure 3-12, page 92.

Updated Table B-1 and added Table B-2.

02/16/2012 1.4 Replaced “clocking backbone” with “clock backbone” and “clocking region” with “clock

region” throughout.

Added Chapter 1, Clocking Overview, containing 7 Series FPGAs Clocking Differences

from Previous FPGA Generations from Chapter 2 and Summary of Clock Connectivity

from Appendix B. Updated Table 1-1. Removed XC7A8, XC7A15, XC7A30T, and

XC7A50T from Table 1-2.

Added Clock-Capable Inputs. Updated Global Clocking Resources, including BUFMR

Primitive. Updated Horizontal Clock Buffer—BUFH, BUFHCE. Updated paragraph

before Figure 2-27.

7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.14) July 30, 2018

02/16/2012 1.4

(Cont’d)

In introductory paragraph of High-Performance Clocks, removed description of HPCs

connecting to OSERDES and buffers. Replaced cross reference to UG429, 7 Series FPGAs

Migration Methodology Guide, with UG872

, Large FPGA Methodology Guide. Updated

Stacked Silicon Interconnect Clocking. Replaced SRL with SLR in Figure 2-29. Added

Figure 2-31.

Removed hold block from Figure 3-2. Updated clock frequencies in Frequency Synthesis

Only Using Integer Divide. Replaced 64 with 63 in Equation 3-4. Updated Interpolated

Fine Phase Shift in Fixed or Dynamic Mode in the MMCM. Updated pin description of

LOCKED in Table 3-5. Updated LOCKED. In Table 3-7, updated type and allowed

values of CLKOUT[0]_DIVIDE_F and CLKFBOUT_MULT_F, and description of

STARTUP_WAIT and COMPENSATION. In Table 3-8, added STARTUP_WAIT and

updated description of COMPENSATION. Replaced GTX with GT in Figure 3-10.

Updated Dynamic Reconfiguration Port.

Added Appendix B, Clocking Resources and Connectivity Variations per Clock Region.

07/13/2012 1.5 Updated paragraph after Figure 1-4. Added bullet about spread spectrum support to

Key Differences from Virtex-6 FPGAs. Updated BUFG and BUFH pins, and removed

IBUFDS_GTE2.O/IBUFDS_GTE2.ODIV2 pin from Table 1-1. Updated Table 1-2.

Updated note 5 in Table 2-1. Added Figure 2-29.

Updated last sentence of Introduction. Updated DO[15:0] – Dynamic Reconfiguration

Output Bus. Added SS_EN, SS_MODE, and SS_MOD_PERIOD to Table 3-7. Added

Spread-Spectrum Clock Generation.

10/02/2012 1.6 Added note to Table 1-1. Removed XC7A350T and XC7V1500T from Table 1-2.

Updated first paragraph of Single Clock Driving Multiple CMTs. Added notes 5 and 8 to

Table 2-1. Updated paragraph after Table 2-10.

Added Table 3-9 and timing constraint calculations for 25 MHz and 80 MHz input

clocks. In Table 3-10, changed Bandwidth value from N/A to Low, and removed

duplicate paragraph after table.

Removed XC7A350T from title of Figure B-4.

04/03/2013 1.7 Updated Figure 1-3, Figure B-2, and Figure B-3. Added BUFMR to Table 1-1

. Updated

second paragraph in Dynamic Phase Shift Interface in the MMCM. Added note to

Table 2-7.

08/07/2013 1.8 Updated Table 1-2 and Table 3-7. Updated the figure titles for Figure B-2 and Figure B-3.

Updated Clock Buffer Placement.

04/08/2014 1.9 Updated Clock-Capable Inputs and Dynamic Phase Shift Interface in the MMCM.

Updated allowed values and the default value for CLKFBOUT_MULT in Table 3-8.

05/24/2014 1.10 Changed the value of minimum clock regions from six to four in Clocking Architecture

Overview. Added information to MGTREFCLK0 in Table 1-1. Added section on GTZ

Loopback Clock Buffer — BUFG_LB (HT devices only) to Chapter 2. Changed

description of REF_JITTER1 and REF_JITTER2 in Table 3-7 and Table 3-8. Updated first

paragraph in Use Cases.

11/19/2014 1.11 Removed general interconnect from this bulleted list on page 49. Updated the figure

titles for Figure B-2 and Figure B-3.

03/04/2015 1.11.1 Updated Frequency Synthesis Using Fractional Divide in the MMCM, page 73 by

changing

0.125 degrees to 0.125.

06/12/2015 1.11.2 Fixed broken link in three references to 7 Series FPGA Data Sheets on page 73 and page 74.

09/27/2016 1.12 Added the Spartan-7 FPGAs and the Artix-7 (XC7A12T and XC7A25T) devices where

applicable including updating Appendix B. Updated the BUFR Alignment section.

Updated the Automotive Applications Disclaimer.

Date Version Revision

UG472 (v1.14) July 30, 2018 www.xilinx.com 7 Series FPGAs Clocking Resources User Guide

03/01/2017 1.13 Updated the BUFR Alignment section.

07/30/2018 1.14 Updated the example in Determine the Input Frequency section.

Date Version Revision

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