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JEDEC

STANDARD

DDR4 SDRAM

JESD79-4B

(Revision of JESD79-4A, November 2013)

JUNE 2017

JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

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JEDEC Standard No. 79-4B

-i-

1 Scope ............................................................................................................................................................................1

2 DDR4 SDRAM Package Pinout and Addressing ......................................................................................................2

2.1 DDR4 SDRAM Row for X4, X8 and X16..........................................

.............................................................................2

2.2 DDR4 SDRAM Ball Pitch ...............................................................

................................................................................2

2.3 DDR4 SDRAM Columns for X4,X8 and X16..........................................

........................................................................2

2.4 DDR4 SDRAM X4/8 Ballout using MO-207 ......................................

.......................................................................... 2

2.5 DDR4 SDRAM X16 Ballout using MO-207 .......................................

.............................................................................3

2.6 DDR4 SDRAM X32 Ballout using MO-XXX ..............................................

.....................................................................4

2.7 Pinout Description.................................................................

.........................................................................................6

2.8 DDR4 SDRAM Addressing................................................................

.............................................................................7

2.9 DDP Single Rank(SR) x16 from two x8 .................................................

........................................................................9

3 Functional Description .............................................................................................................................................11

3.1 Simplified State Diagram ......................................................

.................................................................................... 11

3.2 Basic Functionality ................................................................

.......................................................................................12

3.3 RESET and Initialization Procedure...............................................

..............................................................................12

3.3.1 Power-up Initialization Sequence .......................................

.......................................................................................12

3.3.2 VDD Slew rate at Power-up Initialization Sequence .................................................................................................13

3.3.3 Reset Initialization with Stable Power .......................................................................................................................14

3.4 Register Definition........................................................................................................................................................14

3.4.1 Programming the mode registers ..............................................................................................................................14

3.5 Mode Register.......................................................................

.......................................................................................17

4 DDR4 SDRAM Command Description and Operation ...........................................................................................28

4.1 Command Truth Table.................................................................

.................................................................................28

4.2 CKE Truth Table ....................................................................

.......................................................................................29

4.3 Burst Length, Type and Order........................................................

..............................................................................30

4.3.1 BL8 Burst order with CRC Enabled ................................................

...........................................................................30

4.4 DLL-off Mode & DLL on/off Switching procedure....................

....................................................................................31

4.4.1 DLL on/off switching procedure .................................................................................................................................31

4.4.2 DLL “on” to DLL “off” Procedure ................................................................................................................................31

4.4.3 DLL “off” to DLL “on” Procedure ................................................................................................................................32

4.5 DLL-off Mode ...............................................................................................................................................................33

4.6 Input Clock Frequency Change ........................................................

...........................................................................34

4.7 Write Leveling .....................................................................

.........................................................................................35

4.7.1 DRAM setting for write leveling & DRAM termination function in that mode .............................................................36

4.7.2 Procedure Description................................................................................................................................................36

4.7.3 Write Leveling Mode Exit............................................................................................................................................37

4.8 Temperature controlled Refresh modes.......................................................................................................................38

4.8.1 Normal temperature mode ( 0°C =< TCASE =< 85°C ) ............................................................................................38

4.8.2 Extended temperature mode ( 0°C =< TCASE =< 95°C ) .........................................................................................38

4.9 Fine Granularity Refresh Mode......................................................

..............................................................................39

4.9.1 Mode Register and Command Truth Table...........

.....................................................................................................39

4.9.2 tREFI and tRFC parameters.......................................................................................................................................40

4.9.3 Changing Refresh Rate..............................................................................................................................................40

4.9.4 Usage with Temperature Controlled Refresh mode...................................................................................................41

4.9.5 Self Refresh entry and exit.........................................................................................................................................41

4.10 Multi Purpose Register................................................................................................................................................41

4.10.1 DQ Training with MPR..............................................................................................................................................41

4.10.2 MR3 definition .........................................................................................................................................................41

4.10.3 MPR Reads .............................................................................................................................................................42

4.10.4 MPR Writes .............................................................................................................................................................44

4.10.5 MPR Read Data format ...........................................................................................................................................47

4.11 Data Mask(DM), Data Bus Inversion (DBI) and TDQS....

............................................................................................52

DDR4 SDRAM STANDARD

Contents

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